Interface Specifications

CON1 is the connection interface to the OBC.

Installed Connector: AXK5S80047YG (Panasonic)

CON2 is the DEBUG interface between the FPGA and TRCH. It implements various debug functions between the FPGA and TRCH via the FT4232H-56Q chip manufactured by FTDI. The channel assignments for the FT4232H are as follows:

Connecting the DEBUG interface to a PC with Vivado installed enables FPGA programming. Therefore, a separate Platform cable USB II is not required.

Some of these functions require enabling/disabling via the user switch (SW1) described later.

Refer to the user switch (SW1) section for details.

Connector: 105017-0001 (Molex)

CON3 is a JTAG interface connected to the OBC’s JTAG port. Since it uses the same signal lines (such as FPGA_TMS) as CON2’s Channel A, it cannot be used simultaneously with CON2. Use CON3 when you want to handle JTAG signals directly without using IC2 (do not confuse with I2C).

The following JTAG cables can be connected:

Supported Connector: TSW-106-07-L-S (Samtec)

CON4 is the TRCH ICSP interface, connected to the OBC’s ICSP port.
The pin layout is compatible with Microchip’s MPLAB PICkits 4 and 5. Using the included dual-ended long pin header allows direct connection to the main unit.

Connector: SSQ-108-02-G-S-RA (Samtec)

CON5 is a CAN communication interface connected to the OBC’s CAN port.
It enables communication with the TRCH and FPGA on the OBC.

Connector: TB002-500-03BE (Same Sky)

CON6 is the UIO1 interface, which connects to the OBC’s UIO1 port.
It connects to the FPGA on the OBC and provides signals free for any use.

Supported Connector: SSQ-116-01-G-S (Samtec)

CON7 is the power and GND interface for UIO1.

Supported Connectors: SSQ-103-01-G-S x2 or SSQ-106-01-G-S (Samtec)

CON8 is the UIO2 interface, connected to the UIO2 port on the OBC.
It connects to the FPGA on the OBC and provides signals free for any use.

Supported Connector: SSQ-116-01-G-S (Samtec)

CON9 is the power and GND interface for UIO2.

Supported Connectors: SSQ-103-01-G-S x2 or SSQ-106-01-G-S (Samtec)

CON10 is the Dev Board’s interface for the UIO3, TRCH UART, Watchdog output signal, and External I2C connected to the OBC.
Due to hardware options on the OBC, some signals may be replaced by UIO4. When using these interfaces, be mindful of the differences in power domains.

Supported Connector: SSQ-116-01-G-S (Samtec)

CON11 provides power and GND for the UIO3, TRCH UART, Watchdog output signal, and External I2C. For signals selected for UIO4_XX via the OBC’s hardware options, always use the power from the UIO4 Power & GND Interface (CON13).

Supported Connectors: SSQ-103-01-G-S x2 or SSQ-106-01-G-S (Samtec)

CON12 is the UIO4 interface, which connects to the OBC’s UIO4 port.
It connects to the FPGA on the OBC and provides signals freely available for user use. Mountable Connector: SSQ-116-01-G-S (Samtec)

CON13 is the power supply and GND interface for UIO4.

Supported Connectors: SSQ-103-01-G-S x2 or SSQ-106-01-G-S (Samtec)

When using the SC Bus, the OBC can function as either a host or a device.

CON15 is the SC Bus host interface.
The Data (D+/D-) lines are connected to the OBC and are shared with CON16.
VBUS outputs the voltage directly from CON17, but the voltage drops proportionally to the output current. Furthermore, when a USB plug is inserted into CON16, the power switch on the VBUS path is controlled, disconnecting the VBUS output.
Since simultaneous use of CON15 and CON16 is not intended, do not insert a USB plug into CON16 when using CON15.

Connector: 67643-2911 (Molex)

When using the SC Bus, the OBC can function as either a host or a device.

CON16 is the device interface for the SC Bus.
The Data (D+/D-) lines are connected to the OBC and shared with CON15.
VBUS is connected to the gate of the FET (Q4) that controls the EN terminal of the power switch on the CON15 VBUS path. Therefore, when VBUS is applied, the CON15 VBUS output is disconnected.
Since simultaneous use of CON15 and CON16 is not intended, do not insert a USB plug into CON15 when using CON16.

Connector: 105017-0001 (Molex)

CON17 is the +5V power input interface, utilizing a DC jack.
The corresponding AC adapter plug specification is center positive with an outer diameter of 5.5mm and an inner diameter of 2.1mm.
This serves as the primary power source for all components, including the OBC.

Connector: PJ-002AH (Same Sky)

CON18 is the +5V power input interface, using a 5mm pitch 2-pin terminal block.
It is used in the following cases:

Additionally, by mounting a 0Ω resistor (3216 size) on R110, voltage can be applied directly to the OBC without passing through the power input protection circuit (IC11).

Connector: TB003-500-P02BE (Same Sky)

CON19 is the +5V power supply input interface, using a 5mm pitch 2-pin terminal block.
Use this in the following cases:

Additionally, by mounting a 0Ω resistor (3216 size) on R122, it is possible to apply voltage directly to the OBC without passing through the power input protection circuit (IC12).

Connector: TB003-500-P02BE (Same Sky)

CON20 is the input interface for VDD_UIO1, employing a 5mm pitch 2-pin terminal block.
Use this to set VDD_UIO1 to an arbitrary voltage, rather than using VDD_3V3_IO or VDD_3V3_DCDC.

Connector: TB003-500-P02BE (Same Sky)

CON21 is the input interface for VDD_UIO2, employing a 5mm pitch 2-pin terminal block.
Use this to set VDD_UIO2 at an arbitrary voltage, rather than using VDD_3V3_IO or VDD_3V3_DCDC.

Connector: TB003-500-P02BE (Same Sky)

CON22 is the output interface for VDD_3V3_DCDC. It is intended for uses other than powering VDD_UIO1 and VDD_UIO2. The maximum output current is 2A.

Mountable Connector: 10129378-902001BLF (Amphenol CS)

JP1 is an interface that allows you to enable or disable the 120Ω termination resistor on the CAN bus. The OBC does not have a termination resistor installed.

If you want to add a 120Ω termination resistor to the CAN bus, insert the JP1 jumper and short the pins. If termination is provided elsewhere (other than the Dev Board), remove the jumper socket. When the Dev Board is shipped, a jumper socket is inserted on JP1 by default.

Connector: 10129378-902001BLF (Amphenol CS)

JP2 is the interface to switch the power input for VIN_A between CON17 or CON18.

Connector: 10129378-903001BLF (Amphenol CS)

JP3 is the interface to switch the power input for VIN_B between CON17 or CON19.

Connector: 10129378-903001BLF (Amphenol CS)

JP4 is the interface that allows power input for VDD_UIO1 to be selected from VDD_3V3_IO, VDD_3V3_DCDC, or CON20.
The default configuration of the Dev Board is set to VDD_3V3_IO via the jumper socket.

Connector: 10129381-906001BLF (Amphenol CS)

JP5 is the interface that allows power input for VDD_UIO2 to be selected from VDD_3V3_IO, VDD_3V3_DCDC, or CON21.
The default configuration of the Dev Board is set to VDD_3V3_IO via the jumper socket.

Connector: 10129381-906001BLF (Amphenol CS)

SW1 is the switch that controls the connection between the OBC and the following circuits:

In the default configuration, only Bits 3 and 4 are ON; all other bits are OFF. Manually switch the bit that corresponds to the circuit you wish to use.
Use a pointed tool, like tweezers, as it is difficult to operate the switch with your fingers.
The signal line connecting the OBC to SW1 also branches out to the Universal Area. Please be careful when using signal lines connected to the above circuits in the Universal Area.

Parts mounted: 219-10MSTR (CTS Electrocomponents)

SW2 controls the EN pins of the power input protection circuits (IC11, IC12), providing an interface to connect or disconnect CON17~19 from VIN_A and VIN_B.
Moving the SW2 toggle toward the ‘ON’ side (as indicated by the silk screen on the Dev Board) connects the circuit; moving it toward the ‘OFF’ side disconnects it.
The default configuration is ‘OFF’.

Component: SSSF011700 (Alps Alpine)

LED1~8 are status LEDs for each power supply. Illumination indicates a normal status.

Component: SML-D12M8WT86 (ROHM)

LED11 is a user-programmable LED.

Component: SML-D12M8WT86 (ROHM)

Any voltage can be applied to VDD_UIO1 and VDD_UIO2 for use.
However, the FPGA’s IO power supply must follow the FPGA power-up sequence. Applying voltage after VDD_3V3_IO goes High ensures compliance with the power-up sequence.
The Dev Board incorporates power switches (IC14, IC15) on the VDD_UIO lines to prevent applying FPGA IO voltage without adhering to the power sequence.
Furthermore, due to voltage and current capacity constraints on VDD_3V3_IO, JP4 and JP5 enable switching the power input to VDD_UIO between the following three patterns:

VDD_UIO = VDD_3V3_IO

VDD_UIO = VDD_3V3_DCDC

VDD_UIO = Block Terminal Input