Definition of Terms

Refers to the SC-OBC Module A1.

Abbreviation for Timing, Reset, Configuration & Health Controller. The OBC employs the PIC16LF877.

Abbreviation for Field Programmable Gate Array. The OBC uses the Artix-7 from AMD, formerly Xilinx.

Refers to the SC-OBC Module A1 Development Board.

Refers to the area on the Dev Board containing a group of unconnected through-holes arranged at a 2.54 mm pitch.

Refers to User IO Group 1 within the OBC’s FPGA.

Refers to User IO Group 2 within the OBC’s FPGA.

Refers to User IO Group 3 within the OBC’s FPGA.

Refers to User IO Group 4 within the OBC’s FPGA.

Indicates one side, System A, of the OBC’s redundant power input.

Indicates the other side, System B, of the OBC’s redundant power input.

Indicates a voltage output from the OBC. It is a combined voltage generated from the +5 V inputs to VIN_A and VIN_B and is used by the OBC’s TRCH and other circuits. For details, refer to the OBC power supply circuit configuration.

Indicates a voltage output from the OBC. This voltage is generated after VDD_3V3_SYS passes through additional OBC circuitry and is used by components such as the OBC FPGA. For details, refer to the OBC power supply circuit configuration.

Indicates the +3.3 V output of the buck DC/DC converter circuit, IC13, provided on the Dev Board.

Indicates the power supply to the FPGA bank to which UIO1 belongs.

Indicates the power supply to the FPGA bank to which UIO2 belongs.