Electrical Specifications

Absolute Maximum Ratings

Item Symbol Min Max Units Conditions / Notes

Power Supply Voltage

VIN_5V0

-0.3

6.0

V

Operating temperature

Topr

-40

85

°C

Storage temperature

Tstg

-40

85

°C

Versal FPGA​ [1]

Battery power supply voltage

VCC_BATT_IN

-0.500

1.650

V

PL HDIO Bank 302 supply voltage

VCCO_302_IN

-0.500

3.630

V

LPD MIO Bank 502 supply voltage

VCCO_502_IN

-0.500

3.630

V

PL XPIO Bank 703 supply voltage

VCCO_703_IN

-0.500

1.650

V

PL HDIO Bank 302 I/O input voltage

HDIO_302_xxx

-0.550

VCCO_302_IN + 0.550

V

PMC MIO 0/1 I/O input voltage

PMC_500_MIOxx PMC_501_MIOxx

-0.550

VCCO_500_501_OUT + 0.200

V

LPD MIO Bank 502 I/O input voltage

LPD_502_MIOxx

-0.550

VCCO_502_IN + 0.550

V

PL XPIO Bank 703 I/O input voltage

XPIO_703_xxx

-0.550

VCCO_703_IN + 0.550

V

Available output current

IDC

-20

20

mA

Available RMS output current

IRMS​

-20

20

mA

Junction temperature

Tj_versal

-

125

°C

IGLOO2 FPGA

MSIO 0/1 supply voltage

M2GL_VDDI5_IN M2GL_VDDI8_IN

-0.3

3.63

V

MSIO 0/1 input voltage

M2GL_MSIOxxxPBx M2GL_MSIOxxxNBx

-0.3

3.63

V

Junction temperature

Tj_igloo2

-55

135

°C

Recommended Operating Conditions

Item Symbol Min Typ Max Units Conditions / Notes

Power supply voltage

VIN_5V0

4.75

-

5.5

V

Operating temperature

Topr

-40

-

80

°C

Versal FPGA

Battery power supply voltage

VCC_BATT_IN

1.200

-

1.500

V

PL HDIO Bank 302 supply voltage [2]

VCCO_302_IN

1.710

-

3.400

V

LPD MIO Bank 502 supply voltage [2]

VCCO_502_IN

1.710

-

3.400

V

PL XPIO Bank 703 supply voltage [2]

VCCO_703_IN

0.950

-

1.575

V

PL HDIO Bank 302 I/O input voltage

HDIO_302_xxx

-0.200

-

VCCO_302_IN + 0.200

V

PMC MIO 0/1 I/O input voltage

PMC_500_MIOxx PMC_501_MIOxx

-0.200

-

VCCO_500_501_OUT + 0.200

V

LPD MIO Bank 502 I/O input voltage

LPD_502_MIOxx

-0.200

-

VCCO_502_IN + 0.200

V

PL XPIO Bank 703 I/O input voltage

XPIO_703_xxx

-0.200

-

VCCO_703_IN + 0.200

V

VIN overshoot above VCCO and undershoot below GND can reduce the performance of VREF-based receivers within the same nibble.

Junction temperature

Tj_versal

-40

-

100

°C

IGLOO2 FPGA

MSIO 0/1 supply voltage [3]

M2GL_VDDI5_IN M2GL_VDDI8_IN

VDDI x 0.95

VDDI

VDDI x 1.05

V

VDDI is one of the following. 1.2V/1.5V/1.8V/2.5V DC supply voltage

3.15

3.3

3.45

V

3.3V DC supply voltage or LVPECL differential I/O

2.375

2.5

3.45

V

LVDS differential I/O

2.375

2.5

2.625

V

B-LVDS, M-LVDS, Mini-LVDS, RSDS differential I/O

Junction temperature

Tj_igloo2

-40

25

100

°C

Electrical Properties

Item Symbol Min Typ Max Units Conditions / Notes

Output voltage from B to B connector

VDD_1V2_OUT

1.164

1.2

1.236

V

VDD_1V8_OUT

1.746

1.8

1.854

V

VDD_3V3_OUT

3.201

3.3

3.399

V

VCCO_500_501_OUT

1.746

1.8

1.854

V

VCCO_503_OUT

1.746

1.8

1.854

V

M2GL_VDDI4_OUT

1.746

1.8

1.854

V
1. Please refer to the Versal AI Edge Series Data Sheet: DC and AC Switching Characteristics (DS958) for the absolute maximum ratings related to GTYP.
2. For Versal XPIO and HDIO operation, see the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010). PSIO includes PMC dedicated I/O banks, PMC MIO banks, and LPD MIO banks. For PSIO operation, see the Versal Adaptive SoC Technical Reference Manual (AM011) .
3. For IGLOO2 MSIO operation, see the IGLOO2 FPGA and SmartFusion2 SoC FPGA.